Static random access memory (SRAM) and dynamic RAM (DRAM) are volatile memory devices that allow high-speed access and have relatively small capacities. NAND electrically erasable and programmable read only memory (EEPROM) or hard disk drives (HDDs) are nonvolatile memory or storage that have relatively large capacities, but access speeds are slow. Access speeds of NAND EEPROMs or HDDs are slower by about 1000 times of SRAMs or DRAMs.
Accordingly, development of nonvolatile memory that operates at access speeds of speeds between those SRAMs/DRAMs and NAND EEPROMs/HDDs is under way and are called storage class memory (SCM) in this specification.
For SCMs, executing writing attempts for a predetermined number of times even though the data writing fails is considered a desirable function. In this case, however, once the number of write failures exceeds a predetermined number of times, a write fault occurs, and thus recorded data maybe reset and/or lost and, CPUs or memory controllers may not appropriately track write data and the addresses of write destinations of the write data.